The invention relates to signal processing systems, and, more particularly to an analog/digital converter capable of outputting a thermometric digital code.
The ever expanding applications of digital signal processing in place of the traditionally analog processing, requires the conversion of analog signals into digital signals. Processing of high frequency signals requires analog/digital converters with adequately high speed characteristics. The speed and reliability requirements, in terms of statistical incidence of conversion imprecisions, of modern processing systems raise important technological and circuit design problems for overcoming critical functioning behavior of the converters which are often required to function at the limit of their stability characteristics, and wherein metastability phenomena may significantly affect the number of errors of conversion.
The phenomena of metastability in comparators used in an analog/digital converter may cause glitches on the output digital code (word). Glitches may affect correct data processing downstream of the of analog-digital converter. Since the number of errors is exponentially correlated to the clock frequency and to the regenerative time constant of the comparators, the metastability errors may increase in number by several orders of magnitude upon increasing the clock frequency and/or decreasing the supply voltage.
Many techniques have been proposed and developed to reduce the number of errors due to metastability phenomena of the comparators of an analog/digital converter, in order to ensure that the errors remain below a certain limit which, in some applications, may be fixed at a number below 10xe2x88x9210 errors/cycles. The enhancement of the performance of comparators employed in a converter is an approach that ceases to be effective when operating at the technological limits of integration and of minimization of the silicon requirement and/or of power consumption.
In view of these limits, the proposed techniques include introducing latch arrays in cascade (pipelining) of the comparators"" outputs in order to increase the resolution time of the comparators. The pipelining technique, while being capable of decisively reducing the number of errors, increases the circuit complexity. In other words, the pipelining technique may increase the required silicon area and the current absorption. Moreover, this approach necessitates a strict correlation between the increment of the complexity of the pipelining circuits downstream of the array of comparators and their performance in terms of their ability of reducing the number of errors. The article: xe2x80x9cPower-efficient metastability error reduction in CMOS flash A/D convertersxe2x80x9d by C. L. Portmann, T. H. Meng, IEEE Journal of solid state circuits, Vol. 31, No. 8, August 1996, offers a review of the different known techniques of this type.
Typically, modern high speed flash analog/digital converters (flash ADC) include an array of comparators for producing a thermometric code and an array of NOR gates for outputting only a single xe2x80x9c1xe2x80x9d among all xe2x80x9c0sxe2x80x9d to a NOR plane or circuit of a programmable logic array (PLA) are employed, as schematically shown in FIG. 1. As such, the above mentioned article purports the use of three-input NOR cells rather than two-input NOR cells so that the third input may be used as a common mode reference input, by selecting a value higher than the output common mode value of the comparators as a reference.
However, in flash ADCs using high speed bipolar devices, the output dynamic of the comparators may be of a few thermal potentials, thereby, the margin of noise reduction that may be obtained by implementing a common mode circuit, according to the technique suggested in the above cited article, is practically rather limited.
In order to improve immunity to noise and imprecision of the common mode circuit, an effective approach has now been found based on the use of a passive interface at the output of the array of comparators. In practice, this approach realizes a logic that may be defined as pseudo-differential compared to the differential logic of the known circuits.
Specifically, the flash ADC of the invention comprises an array or bank of comparators having a differential output and generating a thermometric code, a bank of three-input logic NOR gates, and a passive interface constituted by voltage dividers. Each voltage divider is connected between the noninverted output of a respective comparator and the inverted output of the comparator of higher order. The respective NOR gate has a first input coupled to the inverted output of the respective comparator, a second input coupled to the noninverted output of the comparator of higher order and a third input coupled to a intermediate node of the voltage divider connected between the noninverted output of the respective comparator and the inverted output of the comparator of higher order.
The passive interface comprising the plurality of voltage dividers decisively increases the immunity to common mode disturbances and noise without sensibly increasing the area requirement or the power consumption.